Description
SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for design, assertions, synthesis and verification. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a complete Object-Oriented paradigm features. There are also considerable improvements in the usability of Verilog for RTL design. In this course we cover the basics of IEEE 1800 - SystemVerilog. Topics covered will be useful for both RTL designers and verification engineers as it covers the basics. As a basic course this does not go in-depth into Synthesis related details, that shall be covered in an advanced course later. ObjectivesTo explore the new features of SystemVerilog for RTL design and demonstrate the improvements in modeling with SVAlso introduce audience to new complex aggregate data types that assist in advanced scoreboards, reference models etc. for verification and modeling. PrerequisitesAttendees must be familiar with Verilog and ideally, but not essentially, Verilog-2001. No prior knowledge of SystemVerilog is required. Digital design fundamentals is a must pre-requisite. Following topics are covered:1. Introduction to SystemVerilogLanguage evolutionSV DesignSV AssertionsSV testbenchDPIAPI2. Introduction to SystemVerilog2. Data types, procedural constructs - enhancementsData types, type checking, type castEnhanced always, case/if. else, loop, flow3. Aggregate data types - arraysEnhancements to static/fixed Arrays from Verilog-2001Multi-dimensional arrays, system functionsDynamic arraysAssociative arraysQueuesArray query operators4. Packages, port connectionsPackagesEnhanced port connection styles5. Interfaces in SystemVerilogInterface - Grouping signalsModportClocking block
